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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. 128kx16 sram/flash module, smd 5962-96900 features access times of 35ns (sram) and 70ns (flash) access times of 70ns (sram) and 120ns (flash) packaging ? 66-pin, pga type, 1.075 inch square hip, hermetic ceramic hip (package 400) ? 66-pin, pga type, 1.185 inch square hip, hermetic ceramic hip (package 401) ? 68 lead, hermetic cqfp (g1u) 1 , 22.4mm (0.880 inch) square (package 519). designed to ? t jedec 68 lead 0.990 cqfj footprint (figure 2) ? 68 lead, hermetic cqfp (g1t), 22.4mm (0.880 inch) square (package 524) 128kx16 sram 128kx16 5v flash organized as 128kx16 of sram and 128kx16 of flash memory with separate data buses both blocks of memory are user con? gurable as 256kx8 low power cmos commercial, industrial and military temperature ranges ttl compatible inputs and outputs built-in decoupling caps and multiple ground pins for low noise operation weight ? wsf128k16-xhx 13 grams typical ? wsf128k16-h1x 13 grams typical ? wsf128k16-xg1ux 1 5 grams typical ? wsf128k16-xg1tx 5 grams typical flash memory features 10,000 erase/program cycles sector architecture ? 8 equal size sectors of 16k bytes each ? any combination of sectors can be concurrently erased. also supports full chip erase 5 volt programming; 5v 10% supply embedded erase and program algorithms hardware write protection page program operation and internal program control time. note: for programming information refer to flash programming 1m5 application note. note 1: package not recommended for new designs block diagram pin description fd0-15 flash data inputs/outputs sd0-15 sram data inputs/outputs a0-16 address inputs swe1-2# sram write enable scs1-2# sram chip selects oe# output enable v cc power supply gnd ground nc not connected fwe1-2# flash write enable fcs1-2# flash chip select top view figure1 pin configuration for wsf128k16-xhx and wsf128k16-xh1x 11223 344556 11 22 33 44 55 66 fd 8 fd 9 fd 10 a 6 a 7 nc a 8 a 9 fd 0 fd 1 fd 2 fd 15 fd 14 fd 13 fd 12 a 0 a 1 a 2 fd 7 fd 6 fd 5 fd 4 sd 15 sd 14 sd 13 sd 12 oe# nc swe 1 # sd 7 sd 6 sd 5 sd 4 swe 2 # scs 2 # gnd sd 11 a 10 a 11 a 12 v cc scs 1 # nc sd 3 v cc fcs 2 # fwe 2 # fd 11 a 3 a 4 a 5 fwe 1 # fcs 1 # gnd fd 3 sd 8 sd 9 sd 10 a 13 a 14 a 15 a 16 nc sd 0 sd 1 sd 2 128k x 8 sram 128k x 8 sram 128k x 8 flash 128k x 8 flash 8 sd 0-7 swe 1 # scs 1 # swe 2 # scs 2 # fwe 1 # fcs 1 # fwe 2 # fcs 2 # 8 sd 8-15 8 fd 0-7 8 fd 8-15 a 0-16 oe#
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. top view figure 2 C pin configuration for wsf128k16-xg1ux 1 , wsf128k16-xg1tx block diagram 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 sd 0 sd 1 sd 2 sd 3 sd 4 sd 5 sd 6 sd 7 gnd sd 8 sd 9 sd 10 sd 11 sd 12 sd 13 sd 14 sd 15 v cc a 11 a 12 a 13 a 14 nc nc scs 1 # oe# scs 2 # nc swe 2 # fwe 3 # fwe 4 # nc nc nc fd 0 fd 1 fd 2 fd 3 fd 4 fd 5 fd 6 fd 7 gnd fd 8 fd 9 fd 10 fd 11 fd 12 fd 13 fd 14 fd 15 nc a 0 a 1 a 2 a 3 a 4 a 5 fcs 3 # gnd fcs 4 # swe 1 # a 6 a 7 a 8 a 9 a 10 v cc 128k x 8 sram 128k x 8 sram 128k x 8 flash 128k x 8 flash 8 sd 0-7 swe 1 # scs 1 #swe 2 # scs 2 #fwe 1 # fcs 1 #fwe 2 # fcs 2 # 8 sd 8-15 8 fd 0-7 8 fd 8-15 a 0-16 oe# note 1: package not recommended for new designs pin description fd0-15 flash data inputs/outputs sd0-15 sram data inputs/outputs a0-16 address inputs swe1-2# sram write enable scs1-2# sram chip selects oe# output enable v cc power supply gnd ground nc not connected fwe1-2# flash write enable fcs1-2# flash chip select
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. dc characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo scs# = v ih , oe# = v ih , v out = gnd to v cc 10 a sram operating supply current x 16 mode i ccx16 scs# = v il , oe# = fcs# = v ih , f = 5mhz, v cc = 5.5 360 ma standby current i sb fcs# = scs# = v ih , oe# = v ih , f = 5mhz, v cc = 5.5 40 ma sram output low voltage v ol i ol = 2.1ma, v cc = 4.5 0.4 v sram output high voltage v oh i oh = -1.0ma, v cc = 4.5 2.4 v flash v cc active current for read (1) i cc1 fcs# = v il , oe# = scs# = v ih 100 ma flash v cc active current for program or erase (2) i cc2 fcs# = v il , oe# = scs# = v ih 130 ma flash output low voltage v ol i ol = 8.0ma, v cc = 4.5 0.45 v flash output high voltage v oh1 i oh = -2.5 ma, v cc = 4.5 0.85 x v cc v flash output high voltage v oh2 i oh = -100 a, v cc = 4.5 v cc -0.4 v flash low v cc lock out voltage v lko 3.2 v notes: 1. the icc current listed includes both the dc operating current and the frequency dependent component (@ 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe# at v ih . 2. icc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions: v il = 0.3v, v ih = v cc - 0.3v absolute maximum ratings parameter symbol min max unit operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 7.0 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v parameter flash data retention 10 years flash endurance (write/erase cycles) 10,000 notes: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v sram truth table scs# oe# swe# mode data i/o power h x x standby high z standby l l h read data out active l h h read high z active l x l write data in active capacitance t a = +25c test symbol condition max unit oe# capacitance c oe v in = 0v, f = 1.0mhz 50 pf f/s we1-2# capacitance c we v in = 0v, f = 1.0mhz 20 pf f/s cs1-2# capacitance c cs v in = 0v, f = 1.0mhz 20 pf sd0-15/fd0-15 capacitance c i/o v in = 0v, f = 1.0mhz 20 pf a0 - a16 capacitance c ad v in = 0v, f = 1.0mhz 50 pf this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. sram ac characteristics v cc = 5.0v, -55c t a +125c parameter read cycle symbol -35 -70 unit min max min max read cycle time t rc 35 70 ns address access time t aa 35 70 ns output hold from address change t oh 03ns chip select access time t acs 35 70 ns output enable to output valid t oe 20 35 ns chip select to output in low z t clz 1 33ns output enable to output in low z t olz 1 00ns chip disable to output in high z t chz 1 20 25 ns output disable to output in high z t ohz 1 20 25 ns 1. this parameter is guaranteed by design but not tested. sram ac characteristics v cc = 5.0v, -55c t a +125c parameter write cycle symbol -35 -70 unit min max min max write cycle time t wc 35 70 ns chip select to end of write t cw 25 60 ns address valid to end of write t aw 25 60 ns data valid to end of write t dw 20 30 ns write pulse width t wp 25 50 ns address setup time t as 05ns address hold time t ah 05ns output active from end of write t ow1 45ns write enable to output in high z t whz1 20 25 ns data hold from write time t dh 00ns 1. this parameter is guaranteed by design but not tested. figure 3 ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 ? . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. address data i/o read cycle 1 (scs# = oe# = v il , swe# = v ih ) t aa t oh t rc data valid previous data valid address data i/o read cycle 2 (swe# = v ih ) t aa t acs t oe t clz t olz t ohz t rc data valid high impedance scs# soe# t chz address data i/o write cycle 2, scs# controlled t aw t as t cw t ah t wp t dh t dw t wc scs# swe# data valid figure 4 C sram timing waveform read cycle figure 6 C sram write cycle scs# controlled address data i/o write cycle 1, swe# controlled t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid scs# swe# figure 5 C sram write cycle swe# controlled
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. flash ac characteristics C write/erase/program operations, fwe# controlled v cc = 5.0v, -55c t a +125c parameter symbol -70 -120 unit min max min max write cycle time t avav t wc 70 120 ns chip select setup time t elwl t cs 00ns write enable pulse width t wlwh t wp 35 50 ns address setup time t avwl t as 00ns data setup time t dvwh t ds 30 50 ns data hold time t whdx t dh 00ns address hold time t wlax t ah 45 50 ns chip select hold time t wheh t ch 00ns write enable pulse width high t whwl t wph 20 20 ns duration of byte programming operation (min) t whwh1 14 14 s chip and sector erase time t whwh2 2.2 60 2.2 60 sec read recovery time before write t ghwl 00s v cc set-up time t vcs 50 50 s chip programming time 12.5 12.5 sec output enable setup time t oes 00ns output enable hold time (1) t oeh 10 10 ns 1. for toggle and data# polling. flash ac characteristics C read only operations v cc = 5.0v, -55c t a +125c parameter symbol -70 -120 unit min max min max read cycle time t avav t rc 70 120 ns address access time t avqv t acc 70 120 ns chip select access time t elqv t ce 70 120 ns oe# to output valid t glqv t oe 35 50 ns chip select to output high z (1) t ehqz t df 20 30 ns oe# high to output high z (1) t ghqz t df 20 30 ns output hold from address, cs# or oe# change, whichever is ? rst t axqx t oh 00ns 1. guaranteed by design, not tested.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. flash ac characteristics C write/erase/program operations, fcs# controlled v cc = 5.0v, -55c t a +125c parameter symbol -70 -120 unit min max min max write cycle time t avav t wc 70 120 ns fwe# setup time t wlel t ws 00ns fcs# pulse width t eleh t cp 35 50 ns address setup time t avel t as 00ns data setup time t dveh t ds 30 50 ns data hold time t ehdx t dh 00ns address hold time t elax t ah 45 50 ns fwe# hold from fwe# high t ehwh t wh 00ns fcs# pulse width high t ehel t cph 20 20 ns duration of programming operation t whwh1 14 14 s duration of erase operation t whwh2 2.2 60 2.2 60 sec read recovery before write t ghel 00ns chip programming time 12.5 12.5 sec
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 7 C ac waveforms for flash memory read operations addresses fcs# oe# fwe# outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 8 C write/erase/program operation, flash memory fwe# controlled notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7# is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. addresses fcs# oe# fwe# data 5.0 v 5555h pa pa t wc t cs pd d 7 # d out t ah t wph t dh t ds data# polling t as t rc t wp a0h t oe t df t oh t ce t ghwl t whwh1
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 9 C ac waveforms chip/sector erase operations for flash memory note: sa is the sector address for sector erase. addresses fcs# oe# fwe# data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t as t ghwl t wph t dh t ds
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 10 C ac waveforms for data# polling during embedded algorithm operations for flash memory fcs# oe# fwe# t oe t oe d7 d7 valid data t ce t ch t oh high z d7# d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d7 d0-d6 t oeh t whwh 1 or 2 t whwh 1 or 2
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 11 C write/erase/program operation for flash memory, cs# controlled notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d7# is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. addresses fwe# oe# fcs# data 5.0 v 5555h pa pa t wc t ws pd d 7 # d out t ah t cph t cp t dh t ds data# polling t as t ghel a0h t whwh1
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 400: 66 pin, pga type, ceramic hex-in-line package, hip (h1) all linear dimensions are millimeters and parenthetically in inches
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. all linear dimensions are millimeters and parenthetically in inches note 1: package not recommended for new designs package 519: 68 lead, ceramic quad flat pack, cqfp (g1u) 1
15 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. all linear dimensions are millimeters and parenthetically in inches 23.88 (0.940) 0.25 (0.010) sq 25.27 (0.995) 0.13 (0.005) sq 4.06 (0.160) max 0.25 (0.010) max 0.84 (0.033) ref detail a 0.83 (0.033) 0.32 (0.013) see detail "a" 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) ref 1.27 (0.050) package 524: 68 lead, ceramic quad flat pack, low profile cqfp (g1t)
16 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wsf128k16-xxx may 2003 rev. 6 white electronic designs corp. reserves the right to change products or speci? cations without notice. lead finish: blank = gold plated leads a = solder dip leads device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h1 = 1.075" sq. ceramic hex in-line package, hip (package 400) h = 1.185" sq. ceramic hex in-line package, hip (package 401) g1u = 22.4 mm ceramic quad flat pack, cqfp (package 519) g1t = 22.4mm ceramic quad flat pack, cqfp (package 524) access time (ns) 37 = 35ns sram and 70ns flash 72 = 70ns sram and 120ns flash organization, 128k x 16 flash sram white electronic designs corp. ordering information w s f 128k16 - xxx x x x device type sram speed flash speed package smd no. 128k x 16 mixed module 70ns 120ns 66 pin hip (h) 5962-96900 01hxx 128k x 16 mixed module 70ns 120ns 66 pin hip (h1) 5962-96900 01hyx 128k x 16 mixed module 70ns 120ns 68 lead cqfp/j (g1u) 5962-96900 01h9x 128k x 16 mixed module 35ns 70ns 66 pin hip (h) 5962-96900 02hxx 128k x 16 mixed module 35ns 70ns 66 pin hip (h1) 5962-96900 02hyx 128k x 16 mixed module 35ns 70ns 68 lead cqfp/j (g1u) 5962-96900 02h9x

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